EP1S25F780I6N

Product Summary

The EP1S25F780I6N is a member of the StratixR family of FPGAs that is based on a 1.5-V, 0.13- μm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. The Stratix device offers up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. It supports various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).

Parametrics

Absolute maximum ratings: (1)VCCINT, Supply voltage With respect to ground: –0.5 to 2.4 V; (2)VCCIO, Supply voltage With respect to ground: –0.5 to 4.6 V; (3)VI, DC input voltage: –0.5 to 4.6 V; (4)IOUT, DC output current, per pin: –25 to 40 mA; (5)TSTG, Storage temperature No bias: –65 to 150 ℃; (6)TJ, Junction temperature BGA packages under bias: 135 ℃ max.

Features

Features: (1)10,570 to 79,040 LEs; see Table 1.1; (2)Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources; (3)TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers; (4)High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters; (5)Up to 16 global clocks with 22 clocking resources per device region; (6)Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting; (7)Support for numerous single-ended and differential I/O standards; (8)High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps); (9)Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4; (10)Differential on-chip termination support for LVDS ; (11)Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM; (12)Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster speed-grade devices; (13)Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices; (14)Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices; (15)Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices; (16)Support for multiple intellectual property megafunctions from Altera MegaCore functions and Altera Megafunction Partners Program (AMPPSM) megafunctions; (17)Support for remote configuration updates.

Diagrams