EPM7128SLC84-10N

Programmable Logic Device, PLCC, 5.0-V in-system programmability, PCI-compliant devices available

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Price:: US $3.39~5.45 / piece [Get Latest Price]

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Qty (lots)	Price/lot
1 ~ 10 :	5.45 / Piece
11 ~ 100 :	4.17 / Piece
101 ~ 500 :	3.39 / Piece

PartNumber:: EPM7128SLC84-10N

Brand:: Altera Corporation - ALTR | Pack: PLCC | D/C: 09+

Availability:: Supply Ability: 1000/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Datasheet:: EPM7128SLC84-10N Datasheet download

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Products Upload time: 2013-01-05

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Part Number:EPM7128SLC84-10N
US $3.39 - 5.45
Quantity:

piece

Product Summary

The EPM7128SLC84-10N is a high-density, high-performance PLD. It is based on Altera second-generation MAX architecture. Fabricated with advanced CMOS technology, the EPM7128SLC84-10N provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. EPM7128SLC84-10N in the -5, -6, -7, and -10 speed grades complies with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Parametrics

EPM7128SLC84-10N absolute maximum ratings: (1)VCC Supply voltage With respect to ground: –2.0 to 7.0 V; (2)VI DC input voltage: –2.0 to 7.0 V; (3)IOUT DC output current, per pin: –25 to 25 mA; (4)TSTG Storage temperature No bias: –65 to 150 ℃; (5)TAMB Ambient temperature Under bias: –65 to 135 ℃; (6)TJ Junction temperature Ceramic packages, under bias: 150 ℃; PQFP and RQFP packages, under bias 135 ℃.

Features

EPM7128SLC84-10N features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices; ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available.