Product Summary

EOL Product<br />
Document No. E0359E20 (Ver. 2.0)<br />
Date Published January 2005 (K) Japan<br />
Printed in Japan<br />
URL: <a href="http://www.elpida.com">http://www.elpida.com</a><br />
?Elpida Memory, Inc. 2003-2005<br />
DATA SHEET<br />
256M bits SDRAM<br />
EDS2516APTA (16M words × 16 bits)<br />
Description<br />
The EDS2516AP is a 256M bits SDRAM organized as<br />
4,194,304 words × 16 bits × 4 banks. All inputs and<br />
outputs are referred to the rising edge of the clock<br />
input. It is packaged in standard 54-pin plastic TSOP<br />
(II)<br />
Features<br />
? 3.3V power supply<br />
? Clock frequency: 166MHz/133MHz (max.)<br />
? LVTTL interface<br />
? Single pulsed /RAS<br />
? ×16 organization<br />
? 4 banks can operate simultaneously and<br />
independently<br />
? Burst read/write operation and burst read/single write<br />
operation capability<br />
? Programmable burst length (BL): 1, 2, 4, 8, full page<br />
? 2 variations of burst sequence<br />
? Sequential (BL = 1, 2, 4, 8, full page)<br />
? Interleave (BL = 1, 2, 4, 8)<br />
? Programmable /CAS latency (CL): 2, 3<br />
? Byte control by UDQM and LDQM<br />
Refresh cycles: 8192 refresh cycles/64ms<br />
? 2 variations of refresh<br />
? Auto refresh<br />
? Self refresh<br />
? 2 types of TSOP (II) package<br />
? Sn-Pb solder<br />
? Lead free solder (Sn-Bi)<br />
Pin Configurations<br />
/xxx indicates active low signal.<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
8<br />
9<br />
10<br />
11<br />
12<br />
13<br />
14<br />
15<br />
16<br />
17<br />
18<br />
19<br />
20<br />
21<br />
22<br />
23<br />
24<br />
25<br />
26<br />
27<br />
54<br />
53<br />
52<br />
51<br />
50<br />
49<br />
48<br />
47<br />
46<br />
45<br />
44<br />
43<br />
42<br />
41<br />
40<br />
39<br />
38<br />
37<br />
36<br />
35<br />
34<br />
33<br />
32<br />
31<br />
30<br />
29<br />
28<br />
VSS<br />
DQ15<br />
VSSQ<br />
DQ14<br />
DQ13<br />
VDDQ<br />
DQ12<br />
DQ11<br />
VSSQ<br />
DQ10<br />
DQ9<br />
VDDQ<br />
DQ8<br />
VSS<br />
NC<br />
UDQM<br />
CLK<br />
CKE<br />
A12<br />
A11<br />
A9<br />
A8<br />
A7<br />
A6<br />
A5<br />
A4<br />
VSS<br />
VDD<br />
DQ0<br />
VDDQ<br />
DQ1<br />
DQ2<br />
VSSQ<br />
DQ3<br />
DQ4<br />
VDDQ<br />
DQ5<br />
DQ6<br />
VSSQ<br />
DQ7<br />
VDD<br />
LDQM<br />
/WE<br />
/CAS<br />
/RAS<br />
/CS<br />
BA0<br />
BA1<br />
A10<br />
A0<br />
A1<br />
A2<br />
A3<br />
VDD<br />
54-pin plastic TSOP (II)<br />
(Top view)<br />
Address input<br />
Bank select address<br />
Data-input/output<br />
Chip select<br />
Row address strobe<br />
Column address strobe<br />
Write enable<br />
A0 to A12,<br />
BA0, BA1<br />
DQ0 to DQ15<br />
/CS<br />
/RAS<br />
/CAS<br />
/WE<br />
Input/output mask<br />
Clock enable<br />
Clock input<br />
Power for internal circuit<br />
Ground for internal circuit